Dual Broadband RF Transceiver
·Dual transmitters
·Dual receivers
·Support for TDD and FDD applications
·Dual input shared observation receiver
·Maximum receiver bandwidth: 200 MHz
·Maximum tunable transmitter synthesis bandwidth: 450 MHz
·Maximum observation receiver bandwidth: 450 MHz
·Fully integrated fractional-N RF synthesizers
·Fully integrated clock synthesizer
·Multichip phase synchronization for RF LO and baseband clocks
·JESD204B datapath interface
·Tuning range (center frequency): 50 MHz to 6000 MHz
·12 mm x 12 mm, 196-ball FCBGA
EVB
·Zynq-7000 XC7Z045-2FFG900C SoC
·1 GB DDR3 memory on the programmable logic (PL) side
·1 GB DDR3 component memory on the processing system (PS) side
·Two 128 Mb Quad-SPI (QSPI) flash memory (Dual Quad-SPI)
·Secure Digital (SD) connector
·Clock source:
·Fixed 200 MHz LVDS oscillator (differential)
·I2C programmable LVDS oscillator (differential)
·Fixed 33.33 MHz LVCMOS oscillator (single-ended)
·Subminiature version A (SMA) connectors (differential)
·SMA connectors for GTX transceiver clocking (differential)
·two VITA 57.1 FMC HPC connector (eight GTX transceivers)
·Ethernet PHY RGMII interface with RJ-45 connector
·USB-to-UART bridge with mini-B USB connector
·20-pin PL PJTAG header
·8 user leds,4 pushbuttons
·20 gpios
Copyright © 2017-2020 Zealync All Rights Reserved