· Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz

· Noise floor: −156 dBc/Hz at 2457.6 MHz

· Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output

· Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2

· Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz

· JESD204B-compatible system reference (SYSREF) pulses

· 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels

· SPI-programmable phase noise vs. power consumption

· SYSREF valid interrupt to simplify JESD204B synchronization

· Narrow-band, dual core VCOs

· Up to 2 buffered voltage controlled oscillator (VCXO) outputs

· Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes

· Frequency holdover mode to maintain output frequency

· Loss of signal (LOS) detection and hitless reference switching

· 4× GPIOs alarms/status indicators to determine the health of the system

· External VCO input to support up to 6000 MHz

· On-board regulators for excellent PSRR

· 10 mm × 10 mm, 68-lead LFCSP package

ZL7044  High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B