·JESD204B (Subclass 1) coded serial digital outputs
·Support for lane rates up to 16 Gbps per lane
·1.65 W total power per channel at 3 GSPS (default settings)
·Performance at −2 dBFS amplitude, 2.6 GHz input
·SFDR = 70 Dbfs
·SNR = 57.2 dBFS
·Performance at −9 dBFS amplitude, 2.6 GHz input
·SFDR = 78 dBFS
·SNR = 59.5 dBFS
·Integrated input buffer
·Noise density = −152 dBFS/Hz
·0.975 V, 1.9 V, and 2.5 V dc supply operation
·9 GHz analog input full power bandwidth (−3 dB)
·Amplitude detect bits for efficient AGC implementation
·2 integrated, wideband digital processors per channel
·48-bit NCO
4 cascaded half-band filters
·Phase coherent NCO switching
·Up to 4 channels available
·Serial port control Integer clock with divide by 2 and divide by 4 options
·Flexible JESD204B lane configurations
·On-chip dither
·12 mm x 12 mm, 196-ball BGA
ZLAD02 3GSPS, JESD204B, Dual Analog-to-Digital Converter
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