·JESD204B (Subclass 1) coded serial digital outputs

·Support for lane rates up to 16 Gbps per lane

·Noise density

     ·−152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p

     ·−154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p

     ·−154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p

     ·−155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p

·1.55 W total power per channel at 2.56 GSPS (default settings)

·SFDR at 2.56 GSPS encode

      ·73 dBFS at 1.8 GHz AIN at −2.0 dBFS

      ·59 dBFS at 5.53 GHz AIN at −2.0 dBFS

      ·full-scale voltage = 1.1 V p-p

·SNR at 2.56 GSPS encode

      ·59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS

      ·53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS

      ·full-scale voltage = 1.1 V p-p

·SFDR at 2.0 GSPS encode

      ·78 dBFS at 900 MHz AIN at −2.0 dBFS

      ·62 dBFS at 5.53 GHz AIN at −2.0 dBFS

      ·full-scale voltage = 1.1 V p-p

·SNR at 2.0 GSPS encode

      ·62.7 dBFS at 900 MHz AIN at −2.0 dBFS

      ·53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS

      ·full-scale voltage = 1.1 V p-p

·0.975 V, 1.9 V, and 2.5 V dc supply operation

·9 GHz analog input full power bandwidth (−3 dB)

·Amplitude detect bits for efficient AGC implementation

·Programmable FIR filters for analog channel loss equalization

·2 integrated, wideband digital processors per channel

·48-bit NCO

·Programmable decimation rates

·Phase coherent NCO switching

·Up to 4 channels available

·Serial port control

·Supports 100 MHz SPI writes and 50 MHz SPI reads

·Integer clock with divide by 2 and divide by 4 options

·Flexible JESD204B lane configurations

·On-chip dither

·12 mm x 12 mm, 196-ball BGA

ZLAD03  2.6GSPS, JESD204B, Dual Analog-to-Digital Converter